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engineering specification type 15.0 qxga color tft/lcd module model name:IAQX10M document control number : oem i-910m-03 note:specification is subject to change without notice. consequently it is better to contact to international display technology before proceeding with the design of your product incorporating this module. sales support international display technology engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 1/30
i contents i contents ii record of revision 1.0 handling precautions 2.0 general description 2.1 characteristics 2.2 functional block diagram 3.0 absolute maximum ratings 4.0 optical characteristics 5.0 signal interface 5.1 connectors 5.2 interface signal connector 5.3 interface signal description 5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver 5.4.2 lvds receiver internal circuit 5.4.3 recommended guidelines for motherboard pcb design and cable selection 5.5 signal for lamp connector 6.0 pixel format image 7.0 parameter guide line for cfl inverter 8.0 interface timings 8.1 timing characteristics 8.2 timing definition 9.0 power consumption 10.0 power on/off sequence 11.0 mechanical characteristics 12.0 national test lab requirement engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 2/30
ii record of revision based on internal spec. ec h31231 as of may 10,2002. to update handling precautions. to update electrical characteristics. to update switching characteristics. to delete 5.0[ma] lamp condition. to update timing characteristics. 4 13 15 22 24 oem i-910m-03 june 17,2002 based on internal spec. ec h31230 as of february 20,2002. to update handling precautions. to update following items. weight physical size white luminance power consumption (vdd line) lamp power consumption to add note for temperature range. to eliminate optional part in the diagram. to update following items. max. value of response time color chromaticity white luminance (icfl) to update interface signal connector. to update interface signal description. to update signal electrical characteristics for lvds receiver. to add recommended guidelines for motherboard pcb design and cable selection. to update parameter guide line for cfl inverter. to update typ. value of power consumption. to update reference drawings. 4 6 7 9 11 12,13 14-18 19 22 26 28,29 oem i-910m-02 march 12,2002 first edition for customer. based on internal spec. ec h31229 as of november 9,2001. all oem i-910m-01 november 13,2001 summary page document revision date engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 3/30
1.0 handling precautions if any signals or power lines deviate from the power on/off sequence, it may cause shorten the life of the lcd module. the lcd panel and the cfl are made of glass and may break or crack if dropped on a hard surface, so please handle them with care. cmos-ics are included in the lcd panel. they should be handled with care, to prevent electrostatic discharge. do not press the reflector sheet at the back of the lcd module to any directions. do not stick the adhesive tape on the reflector sheet at the back of the lcd module. please handle care when mount in the system cover. mechanical damage for lamp cable and for lamp connector may cause safety problems. small amount of materials having no flammability grade is used in the lcd module. the lcd module should be supplied by power complied with requirements of limited power source (2.5, iec60950 or ul60950), or be applied exemption conditions of flammability requirements (4.7.3.4, iec60950 or ul60950) in an end product. the lcd module is designed so that the cfl in it is supplied by limited current circuit (2.4, iec60950 or ul1950). the fluorescent lamp in the liquid crystal display(lcd) contains mercury. do not put it in trash that is disposed of in landfills. dispose of it as required by local ordinances or regulations. never apply detergent or other liquid directly to the screen. wipe off water drop immediately. long contact with water may cause discoloration or spots. when the panel surface is soiled, wipe it with absorbent cotton or other soft cloth; do not use solvents or abrasives. do not touch the front screen surface in your system, even bezel. the information contained herein may be changed without prior notice. it is therefore advisable to contact international display technology before proceeding with the design of equipment incorporationg this product. the information contained herein is presented only as a guide for the applications of our products. no responsibility is assumed by international display technology for any infringements of patents or other right of the third partied which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of international display technology or others. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 4/30
2.0 general description this specification applies to the type 15.0 color tft/lcd module 'IAQX10M'. this module is designed for a display unit of a monitor application. the screen format and electrical interface are intended to support the qxga(2048(h) x 1536(v)) screen. support color is native 262k colors(rgb 6-bit data driver). all input signals are lvds(low voltage differential signaling) interface compatible. this module does not contain an inverter card for backlight. 2.1 characteristics the following items are characteristics summary on the table under 25 degree c condition: 0 to +50 (note) -20 to +60 temperature range [degree c] operating storage (shipping) 8 pairs lvds(even/odd r/g/b data(6bit), 3sync signals, clock) electrical interface 8.6 typ. (w/o inverter loss) lamp power consumption [watt] icfl=7.0ma 4.1 typ., 5.2 max. power consumption [wa tt](vdd line) +3.3 typ. nominal input voltage vdd [volt] 60 typ. optical rise time + fall time [msec] 400 : 1 typ. contrast ratio 200 typ. (center) 180 typ. (5 points average) white luminance [cd/m 2 ] icfl=7.0ma native 262k colors(rgb 6-bit data driver) support color normally black display mode 326.0(w) x 244.5(h) x 13.0(d) typ./13.3(d) max. physical size [mm] 1065 typ., 1100 max. weight [grams] r,g,b vertical stripe pixel arrangement 0.1485(per one triad) x 0.1485 pixel pitch [mm] 304.1(h) x 228.1(v) active area [mm] 2048(x3) x 1536 pixels h x v 380 screen diagonal [mm] specifications characteristics items note : max. operating temperature 50 degree c in the spec means the temperature measured for the point of the front surface of the lcd glass cell. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 5/30
2.2 functional block diagram the following diagram shows the functional block of this type 15.0 color tft/lcd module. the first lvds port transmits even pixels while the second lvds port transmits odd pixels. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 6/30 x-driver tft array/cell 6bit color data for r/g/b dtclk(even/odd) dsptmg hsync vsync vdd lcd controller lcd drive card backlight unit 2048(r/g/b) x 1536 gnd dc-dc converter ref circuit (even/odd) < 8 pairs lvds > even pixel odd pixel dual lvds receiver lcd-drive connector y-driver g/a lamp connectors jst bhsr-02vs-1 (2pin) x 2 jae fi-xb30s-hf10 (30pin)
3.0 absolute maximum ratings absolute maximum ratings of the module is as follows : rectangle wave g ms 50 18 shock g hz 1.5 10-200 vibration (note 1) %rh 95 5 hst storage relative humidity (note 1) deg.c +60 -20 tst storage temperature (note 1) %rh 95 8 hop operating relative humidity (note 1) deg.c +50 0 top operating temperature ma +20 - icflp cfl peak inrush current mams +8.5 - icfl cfl current (note 2) vrms +1,600 - vs cfl ignition voltage v vdd+0.3 -0.3 vin input signal voltage on all other pins v +2.6 -0.3 - input voltage on flatlink pins v +4.0 -0.3 vdd logic/lcd drive voltage conditions unit max min s y mbol item note 1 : maximum wet-bulb should be 39 degree c and no condensation. note 2 : duration : 50msec max. ta=0 degree c engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 7/30
4.0 optical characteristics the optical characteristics are measured under stable conditions as follows under 25 degree c condition: 200 typ. (center) 180 typ. (5 points average) white luminance (cd/m 2 ) icfl 7.0 ma - 0.329 white y - 0.313 white x - 0.132 blue y - 0.149 blue x - 0.544 green y - 0.312 green x (cie) - 0.332 red y chromaticity - 0.569 red x color 60 max. 30 falling (ms) 60 max. 30 rising response time - 400 contrast ratio - - 85 85 vertical (upper) k 10 (lower) k:contrast ratio - - 85 85 horizontal (right) k 10 (left) viewing angle (degrees) note typ. specification conditions item engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 8/30
5.0 signal interface 5.1 connectors physical interface is described as for the connector on module. these connectors are capable of accommodating the following signals and will be following components. fi-x30m mating receptacle/part number jae mating receptacle manufacture fi-xb30s-hf10 type / part number jae manufacturer for signal connector connector name / designation sm02b-bhss-1 mating type / part number bhsr-02vs-1 type / part number jst manufacturer for lamp connector connector name / designation engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 9/30
5.2 interface signal connector signal connector pin assignment roclkin+ 30 rein2+ 15 roclkin- 29 rein2- 14 gnd 28 gnd 13 roin2+ 27 rein1+ 12 roin2- 26 rein1- 11 gnd 25 gnd 10 roin1+ 24 rein0+ 9 roin1- 23 rein0- 8 gnd 22 vdd 7 roin0+ 21 vdd 6 roin0- 20 reserved (note 1) 5 gnd 19 reserved (note 1) 4 reclkin+ 18 vdd 3 reclkin- 17 vdd 2 gnd 16 gnd 1 signal name pin # signal name pin # note : 1. 'reserved' pins are not allowed to connect any other line. 2. voltage levels of all input signals are lvds compatible (except vdd). refer to "signal electrical characteristics for lvds", for voltage levels of all input signals. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 10/30
5.3 interface signal description the module uses a pair of lvds receiver sn75lvds86(texas instruments) compatible. lvds is a differential signal technology for lcd interface and high speed data transfer device. transmitter shall be sn75lvds84/85 or compatible. positive lvds differential clock input (odd) roclkin+ 30 negative lvds differential clock input (odd) roclkin- 29 ground gnd 28 positive lvds differential data input (odd b2-b5) roin2+ 27 negative lvds differential data input (odd b2-b5) roin2- 26 ground gnd 25 positive lvds differential data input (odd g1-g5, b0-b1) roin1+ 24 negative lvds differential data input (odd g1-g5, b0-b1) roin1- 23 ground gnd 22 positive lvds differential data input (odd r0-r5, g0) roin0+ 21 negative lvds differential data input (odd r0-r5, g0) roin0- 20 ground gnd 19 positive lvds differential clock input (even) reclkin+ 18 negative lvds differential clock input (even) reclkin- 17 ground gnd 16 positive lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2+ 15 negative lvds differential data input (even b2-b5, hsync, vsync, dsptmg) rein2- 14 ground gnd 13 positive lvds differential data input (even g1-g5, b0-b1) rein1+ 12 negative lvds differential data input (even g1-g5, b0-b1) rein1- 11 ground gnd 10 positive lvds differential data input (even r0-r5, g0) rein0+ 9 negative lvds differential data input (even r0-r5, g0) rein0- 8 +3.3v power supply vdd 7 +3.3v power supply vdd 6 reserved reserved 5 reserved reserved 4 +3.3v power supply vdd 3 +3.3v power supply vdd 2 ground gnd 1 description signal name pin # note : 1. input signals of odd and even clock shall be the same timing. 2. the module uses a 100ohm resistor between positive and negative data lines of each receiver input. 3. even: first pixel , odd: second pixel 4. 'reserved' pins are not allowed to connect any other line. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 11/30
ground gnd power supply vdd horizontal sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. hsync (h-s) vertical sync: this signal is synchronized with dtclk. both active high/low signals are acceptable. vsync (v-s) when the signal is high, the pixel data shall be valid to be displayed. +dsptmg (dsp) the signal is used to strobe the pixel +data and the +dsptmg (even/odd) data clock: the typical frequency is 82.125mhz. dtclk blue-pixel data: each blue pixel's brightness data consists of these 6 bits pixel data. (even/odd) blue data 0 (lsb) +blue 0 (eb0/ob0) blue data 1 +blue 1 (eb1/ob1) blue data 2 +blue 2 (eb2/ob2) blue data 3 +blue 3 (eb3/ob3) blue data 4 +blue 4 (eb4/ob4) blue data 5 (msb) +blue 5 (eb5/ob5) green-pixel data: each green pixel's brightness data consists of these 6 bits pixel data. (even/odd) green data 0 (lsb) +green 0 (eg0/og0) green data 1 +green 1 (eg1/og1) green data 2 +green 2 (eg2/og2) green data 3 +green 3 (eg3/og3) green data 4 +green 4 (eg4/og4) green data 5 (msb) +green 5 (eg5/og5) red-pixel data: each red pixel's brightness data consists of these 6 bits pixel data. (even/odd) red data 0 (lsb) +red 0 (er0/or0) red data 1 +red 1 (er1/or1) red data 2 +red 2 (er2/or2) red data 3 +red 3 (er3/or3) red data 4 +red 4 (er4/or4) red data 5 (msb) +red 5 (er5/or5) description signal name note : output signals from any system shall be hi-z state when vdd is off. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 12/30
5.4 interface signal electrical characteristics 5.4.1 signal electrical characteristics for lvds receiver each signal characteristics are as follows; electrical characteristics vth-vtl=200mv [mv] +50 -50 vcm common mode voltage offset vth-vtl=200mv [v] | vid | 2.0 - 2 | vid | 0.6 + 2 vic common mode input voltage [mv] 600 100 |vid| magnitude differential input voltage vcm=+1.2v [mv] -100 vtl differential input low threshold vcm=+1.2v [mv] +100 vth differential input high threshold conditions unit max min symbol parameter note: input signals shall be low or hi-z state when vdd is off. all electrical characteristics for lvds signal are defined and shall be measured at the interface connector of lcd (see figure measurement system). figure. voltage definitions engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 13/30
figure. measurement system engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 14/30
switching characteristics ps 6tc/7+500 6tc/7 6tc/7-500 tlidp2 lvds input data position 7 ps 5tc/7+500 5tc/7 5tc/7-500 tlidp3 lvds input data position 6 ps 4tc/7+500 4tc/7 4tc/7-500 tlidp4 lvds input data position 5 ps 3tc/7+500 3tc/7 3tc/7-500 tlidp5 lvds input data position 4 ps 2tc/7+500 2tc/7 2tc/7-500 tlidp6 lvds input data position 3 ps tc/7+500 tc/7 tc/7-500 tlidp0 lvds input data position 2 fc = 82.125mhz (note 5) ps 500 0 -500 tlidp1 lvds input data position 1 fc = 82.125mhz ns tc/7 tskeoclk skew time between reclkin and roclkin fc = 82.125mhz ps/clk 20 tcjavg cycle modulation rate (note 4) fc = 82.125mhz ps +150 -150 tccj cycle-to-cycle jitter (note 3) ps 500 thd data hold time (note 2) fc = 82.125mhz, tccj < 50ps, vth-vtl=200mv, vcm=1.2v, vcm=0 ps 500 tsu data setup time (note 2) ns 20.0 12.2 11.5 tc cycle time mhz 86.6 82.125 50.0 fc clock frequency conditions unit max typ min symbol parameter note : 1. all values are at vdd=3.3v, ta=25 degree c. 2. see figure "timing definition" and "timing definition(detail a)" for definition. 3. jitter is the magnitude of the change in input clock period. 4. this specification defines maximum average cycle modulation rate in peak-to-peak transition within any 100 clock cycles. this specification is applied only if input clock peak jitter within any 100 clock cycles is greater than 300ps. 5. see figure "lvds input data position". engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 15/30
figure. timing definition (even port) engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 16/30
figure. timming definition (odd port) 5 figure. lvds input data position engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 17/30
figure. timing definition (detail a) note : tsu and thd are internal data sampling window of receiver. trskm is the system skew margin; i.e., the sum of cable skew, source clock jitter, and other inter-symbol interference, shall be less than trskm. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 18/30
5.4.2 lvds receiver internal circuit below figure shows the internal block diagram of the lvds receiver. 5.4.3 recommended guidelines for motherboard pcb design and cable selection following the suggestions below will help to achieve optimal results. use controlled impedance media for lvds signals. they should have a matched differential impedance of 100ohm. match electrical lengths between traces to minimize signal skew. isolate ttl signals from lvds signals. for cables, twisted pair, twinax, or flex circuit with close coupled differential traces are recommended. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 19/30
5.5 signal for lamp connector lamp low voltage 2 lamp high voltage 1 signal name pin # engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 20/30
6.0 pixel format image following figure shows the relationship of the input signals and lcd pixel format image. even and odd pair of rgb data are sampled at a time . r g b r g b r g b r g b r g b r g b r g b r g b even odd even odd 0 1 2047 1st line 1536th line 2046 engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 21/30
7.0 parameter guide line for cfl inverter (ta=25 deg.c) (note 2) w 9.5 8.6 - cfl power consumption(pcfl) (ta=25 deg.c) (note 2) vrms - 620 - cfl voltage (reference)(vcfl) (ta= 0 deg.c) (note 3) vrms - - 1,500 cfl ignition voltage(vs) (ta=25 deg.c) (note 1) khz 60 40 cfl frequency(fcfl) (ta=25 deg.c) marms 7.5 7.0 3.0 cfl current(icfl) (ta=25 deg.c) cd/m 2 - 180 - white luminance (5 points average) condition units max typ min parameter note 1: cfl discharge frequency should be carefully determined to avoid interference between inverter and tft lcd. note 2: calculated value for reference (icfl x vcfl = pcfl). note 3: cfl inverter should be able to give out a power that has a generating capacity of over 1,500 voltage. lamp units need 1,500 voltage minimum for ignition. note 4: all of characteristics listed are measured under the condition using the test inverter. in case of using an inverter other than listed, it is recommended to check the inverter carefully. sometimes, interfering noise stripes appear on the screen, and substandard luminance or flicker at low power may happen. in designing an inverter, it is suggested to check safety circuit very carefully. impedance of cfl, for instance, becomes more than 1 [m ohm] when cfl is damaged. generally, cfl has some amount of delay time after applying kick-off voltage. it is recommended to keep on applying kick-off voltage for 1 [sec] until discharge. reducing cfl current increases cfl discharge voltage and generally increases cfl discharge frequency. so all the parameters of an inverter should be carefully designed so as not to produce too much leakage current from high-voltage output of the inverter. it should be employed the inverter which has 'duty dimming', if icfl is less than 4.0[ma]. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 22/30
the following chart is cfl current versus the luminance for your reference. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 23/30 tbd
8.0 interface timings basically, interface timings described here is not actual input timing of lcd module but output timing of sn75lvds86(texas instruments) or equivalent. 8.1 timing characteristics [dots] 2048 n data even/odd +data [us] 12.469 thd display +dsptmg [tck] 381 8 1 thf h-front porch [tck] 381 32 1 thb h-back porch [tck] 381 8 1 nha [us] 0.097 tha h-active level [tck] 1407 1072 1064 nh [us] - 13.1 - th [khz] - 76.6 - fh scan rate +h-sync [lines] 1536 m v-line +dsptmg [lines] 124 17 1 nvf v-front porch [lines] 124 1 1 nvb v-back porch [lines] 124 1 1 nva [us] - 13.1 - tva v-active level [lines] 1662 1555 1542 nv [ms] - 20.3 - tv [hz] - 49.266 - fv frame rate +v-sync [ns] 20.000 12.177 11.547 tck [mhz] 86.6 82.125 50 fdck freqency dtclk unit max. typ. min. symbol item signal note : both positive hsync and positive vsync polarity is recommended when there are invalid timing, display appears black pattern. synchronous signal defects and enter auto refresh for lcd module protection mode. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 24/30
8.2 timing definition vertical timing 0.013 ms (1 line) 0.013 ms (1 line) 20.298 ms (1555 lines) 0.222 ms (17 lines) 20.050 ms (1536 lines) 0.248 ms (19 lines) 2048 x 1536 at 50hz (h line rate : 13.1 us) tvb vsync back porch tva vsync width tv,nv frame time tvf vsync front porch m active field tvblk vertical blanking support mode tvblk m tvf tva tvb tv dsptmg -vsync +vsync horizontal timing 0.390 us (64 dots) 0.097 us (16 dots) 13.053 us (2144 dots) 0.097 us (16 dots) 12.469 us (2048 dots) 0.584 us (96 dots) 2048 x 1536 dotclock : 164.250 mhz (82.125mhz x2) thb hsync back porch tha hsync width th,nh h line time thf hsync front porch thd active field thblk horizontal blanking support mode thblk thd thf tha thb th dsptmg -hsync +hsync 0 2 4 n-4 n-2 video(even) video(odd) video(even) video(odd) dtclk 1 3 5 n-3 n-1 tck engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 25/30
9.0 power consumption input power specifications are as follows; mvp-p 100 allowable logic/lcd drive ripple noise vddns mvp-p 100 allowable logic/lcd drive ripple voltage vddrp all white pattern vdd=3.3v ma 1240 vdd current idd max pattern vdd=3.0v ma 1730 vdd current idd all white pattern vdd=3.3v w 4.1 vdd power pdd max pattern vdd=3.6v w 5.2 vdd power pdd load capacitance 68uf v 3.6 3.3 3.0 logic/lcd drive voltage vdd condition units max typ min parameter symbol note : max pattern:2 dot vertical sub-pixel stripe. engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 26/30
10.0 power on/off sequence vdd power and lamp on/off sequence is as follows. interface signals are also shown in the chart. signals from any system shall be hi-z state or low level when vdd is off. 90% 10% 10% 10% 90% 10ms max. 0 min. 0 v 0 v vdd signals 180ms min. 0 min. 10% 10% 150ms min. 100ms min. 20ms min. lamp 90% 90% on (recommended). engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 27/30
11.0 mechanical characteristics engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 28/30
engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 29/30
12.0 national test lab requirement the display module is authorized to apply the ul recognized mark. conditions of acceptability this component has been judged on the basis of the required spacings in the standard for safety of information technology equipment, including electrical business equipment, can/csa c22.2 no.950-00,ul60950, 3rd edition, iec 60950 (3rd. ed.) and en 60950 (3rd. ed.), which would cover the component itself if submitted for listing. cf lamp circuit for this model should be supplied from limited current circuit. the units are supplied by limited power sources. the terminals and connectors are suitable for factory wiring only. the terminals and connectors have not been evaluated for field wiring. a suitable electrical and fire enclosure shall be provided. ****** end of page ****** engineering specification (c) copyright international display technology 2001, 2002 all rights reserved. june 17,2002 oem i-910m-03 30/30

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